The present invention relates generally to qualifying integrated circuits and more particularly to a method of qualifying biased integrated circuits on a wafer level.
Many qualification tests for integrated circuits are performed on the die level once the die is mounted into a package. The packaged die is subjected to a qualifying environment and then tested. Because of the different types of housing, the temperature of the qualifying environment may be limited. Similarly, based on the number of dice from a lot which do not qualify, the decision to scrap, retest, or otherwise treat the total lot is made. Thus, if the dice can be tested at the wafer level, the expense of packaging an unacceptable lot is eliminated.
Many of the qualifying tests for environments performed at the die level require biasing of the die while being subject to qualifying environment. Two such tests are the biased burn-in qualification and the radiation hard qualification for gamma ray radiation.
Generally for biased burn-in qualification, the individual dice, after being packaged, go through an initial testing of electrical characteristics. After the initial tests of the packaged unit, they are sent to a biased, high temperature burn-in for approximately 168 hours and then returned for testing of their electrical characteristics. Based on the type of failures occuring after the burn-in, all the dice from a given run are shelved for product engineering and failure analysis or subjected to a recycle of biased burn-in. Ultimately based on the failure rate, the whole run may be scrapped based on the failure of a few parts, generally greater than five percent. If the biased burned-in testing procedures are conducted at the wafer level, the expense of packaging and re-burn-in are eliminated and an earlier decision on scrapping the run at the wafer level can be made.
Generally, integrated circuits are radiation qualified by irradiating the package device, testing it and then annealing to remove the radiation damage. To perform such qualification of integrated circuits on an individual or die basis, is generally expensive. Similarly, because of temperature limitation of the package, the anneal temperature to remove radiation damage is limited. In order to reduce the expense of packaging nonradiation hard circuits, it has been suggested to test the dice and the circuits on a wafer level. U.S. Pat. No. 3,769,693 specifically discusses neutron irradiation and testing on the wafer level with subsequent breaking of the wafer into individual dice and annealing the individual dice. Although addressing neutron radiation, this patent does not discuss a test procedure for total dose gamma ray radiation.
Since the low-dose-rate gamma ray damage takes the form of excessive positive charge generated and ultimately trapped in the circuit passivating dielectric, the nature of the electric fields within the dielectric determine the behavior of the positive charges as they are generated and the net electrical effect of the irradiation upon the circuit. Thus, to properly qualify the circuitry for gamma ray radiation, the integrated circuits must be biased during gamma ray irradiation. This requires a different test procedure than that described in U.S. Pat. No. 3,769,693 for neutron irradiation.